The present invention generally relates to semiconductor devices and more particularly to a semiconductor device having a microstrip line and a fabrication process thereof.
Compound semiconductor devices use a compound semiconductor material for the active part thereof. Because of the very small effective mass of electrons in such compound semiconductor materials, compound semiconductor devices are used extensively for high-speed microwave applications, including portable telephones and satellite telecommunications. In these days, such high-speed compound semiconductor devices are constructed in the form of an MMIC (monolithic microwave integrated circuit) in which an active device such as a GaAs FET is integrated with transmission lines, diodes, resistances, capacitances and inductances, all formed on a common semiconductor substrate. In order to improve the total performance of such MMICs, it is necessary to minimize the loss of passive elements used therein and maximize the maximum tolerable current, in addition to the desired improvement in the performance of individual active devices.
FIG. 1 shows a typical microstrip line used in an MMIC.
Referring to FIG. 1, the microstrip line includes a substrate 11 having a bottom surface covered by a conductor film 12, wherein the substrate 11 carries a conductor pattern 13 on a top surface thereof. In the microstrip line of FIG. 1, it can be seen that the conductor pattern 13 is laterally and vertically surrounded by a dielectric material having different dielectric constants. In such a case, there holds no ideal TEM (transverse electromagnetic wave) mode in the signal transmission through the wiring pattern 13, and generation of higher mode electromagnetic field is inevitable.
When such higher modes are generated, electric fields and magnetic fields are created as represented in FIG. 1 respectively by a continuous line and a broken line, and there appears a frequency dependence in the characteristic impedance or effective dielectric constant of the transmission line.
When a large current is to be transmitted through such a microstrip line, it is desired to reduce the thickness of the substrate 11 as much as possible for facilitating heat dissipation. On the other hand, such a decrease in the thickness of the substrate 11 invites unwanted increase in the capacitance component of the microstrip line impedance. In order to avoid this problem of increased capacitance component, it is necessary to reduce the width of the conductor pattern 13 as much as possible. Thereby, the height of the conductor pattern 13 increases inevitably in order to secure a sufficient cross-sectional area for the conductor pattern 13.
In the construction of the microstrip line of FIG. 1, such an increase in the height of the conductor pattern 13 raises another problem explained hereinafter with reference to FIGS. 2A and 2B.
Referring to FIG. 2A showing the case in which the height of the conductor pattern 13 is small, it will be noted that the electric flux lines exit primarily from the bottom surface of the conductor pattern 13 and reach the conductor film 12 at the bottom of the substrate 11 with the shortest paths. Only a very small number of electric flux lines exit from the top surface of the conductor pattern 13 and reach the conductor film 12.
When the height of the conductor pattern 13 is increased as represented in FIG. 2B, on the other hand, a substantial number of electric flux lines exit not only from the bottom surface of the conductor pattern 13 but also from both side walls thereof and reach the conductor film 12 along curved paths. Thereby, there occurs an increase in the capacitance component of the transmission line impedance.
The structure of FIG. 2B further raises a practical problem in that the formation of the structure of FIG. 2B is difficult. When the structure of FIG. 2B is to be formed, it is necessary to deposit a thick resist film on the substrate 11 and form a groove in the resist film by conducting an exposure and developing process. On the other hand, the exposure of such a thick resist film raises a problem in that the exposure dose tends to become insufficient at the bottom part of the resist film due to the optical absorption of the resist. When this occurs, the interconnection pattern 13 tends to have an inversely tapered cross-sectional form as represented in FIG. 2C. In such a conductor pattern 13 having an inversely tapered cross-sectional form, the number of the electric flux lines exiting from the side walls of the interconnection and reaching the conductor film 12 increases inevitably, and the capacitance component of the transmission line impedance is increased substantially.
In order to overcome the foregoing problem, the Japanese Laid-Open Patent Publication 5-802485 describes a microstrip line as represented in FIG. 3, wherein it can be seen that a thin conductor pattern 13A is formed on the substrate 11 with a width W1, and a thick resist film 14 is deposited on the substrate 11 so as to cover the thin conductor pattern 13A.
Further, the resist film 14 is subjected to an exposure and developing process to form a groove having a width W2 smaller than the width W1. By filling the groove thus formed, a thick conductor pattern 13B is formed on the thin conductor pattern 13A with the width of W2 and with a desired height. In FIG. 3, it should be noted that those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.
On the other hand, the conventional microstrip line of FIG. 3 has a drawback in that, due to the very small thickness of the conductor pattern 13A, it is difficult to form an air bridge structure which is used commonly in the art of MMIC. When an air bridge structure is formed by using the microstrip line of FIG. 3, the conductor pattern 13A easily undergoes a deformation or disconnection in the process of depositing a resist film on the conductor pattern 13A. Thereby, the yield of production of the microstrip line is reduced seriously in the structure of FIG. 3.
Further, the microstrip line of FIG. 3 tends to show the problem of current concentration at the lateral edge part of the conductor pattern 13A as represented in FIGS. 4A and 4B, wherein this problem becomes particularly conspicuous when the microstrip line of FIG. 3 is used to carry GHz-band electric signals. When such a concentration of the electric current occurs, the tall conductor pattern 13B at the center of the thin conductor pattern 13A does not contribute to the transmission of the high-frequency current.
Further, it should be noted that the use of the microstrip line of FIG. 3 in a multilayer interconnection structure shown in FIG. 5 raises another problem in that there is formed a deep depression in the resist film 14 covering an interlayer insulation film 16 when forming an interconnection pattern 13Bxe2x80x2 in correspondence to such a deep depression of the resist film 14 by a damascene process. In the multilayer interconnection structure of FIG. 5, it should be noted that the interlayer insulation film 16 covers a conductor pattern 15 formed on the substrate 11 and there is formed a contact hole 16A in the interlayer insulation film 16 so as to expose the conductor pattern 15. The foregoing deep resist opening is formed so as to expose the contact hole 16A. As represented in FIG. 5, the contact hole 16A is covered by a conductor film 13Axe2x80x2 identical in composition and thickness with the conductor film 13A of the microstrip line of FIG. 3. Thereby, a conductor pattern 13Bxe2x80x2 is formed by an electroplating process so as to fill the deep resist opening. It should be noted that the microstrip line of FIG. 3 is formed at the right side of the conductor pattern 13Bxe2x80x2.
In the structure of FIG. 5, it can be seen that the thickness of the resist film 14 is increased in correspondence to the contact hole 16A as noted above. Thus, the exposure dose tends to become insufficient at the bottom part of the contact hole 16A and a part of the resist film 14 may remain as represented by a numeral 14x. When such a resist fragment 14x remains at the bottom part of the contact hole 16x, the conductor pattern 13Bxe2x80x2 may become defective.
Further, the multilayer interconnection structure of FIG. 5 has a drawback in that the thin conductor pattern 13A or 13Axe2x80x2 is already patterned and it is difficult to grow the thick conductor pattern 13B or 13Bxe2x80x2 thereon by an electroplating process. In order to conduct an electroplating process, it is necessary to supply a current to the conductor pattern 113A or 13Axe2x80x2, while such a supply of the current to the conductor pattern 13A or 13Axe2x80x2 is not possible when the conductor patterns 13A and 13Axe2x80x2 are already patterned.
Accordingly, it is a general object of the present invention to provide a novel and useful semiconductor device having a microstrip line, wherein the foregoing problems are eliminated.
Another and more specific object of the present invention is to provide a microstrip line having a reduced resistance component and a reduced capacitance component suitable for carrying a large electric current and a semiconductor device having such a microstrip line.
Another object of the present invention is to provide a microstrip line, comprising:
a first conductor pattern formed on a substrate;
a second conductor pattern formed on said first conductor pattern with a width substantially identical with a width of said first conductor pattern; and
a third conductor pattern formed on said second conductor pattern with a width smaller than said width of said second conductor pattern.
Another object of the present invention is to provide a semiconductor device, comprising:
a substrate having first and second, mutually opposing principal surfaces;
a conductor layer formed on said substrate so as to cover said second principal surface;
a first conductor pattern formed on said first principal surface of said substrate;
a second conductor pattern formed on said first conductor pattern with a width identical with a width of said first conductor pattern; and
a third conductor pattern formed on said second conductor pattern with a width smaller than said width of said second conductor pattern.
Another object of the present invention is to provide a method of fabricating a semiconductor device having a microstrip line, comprising the steps of:
forming a metal film on a substrate;
forming a first resist pattern on said metal film such that said first resist pattern includes therein a first groove having a first width in conformity with a wiring pattern to be formed;
forming a first conductor pattern on said metal film along said first groove with said first width while using said first resist pattern as a mask;
forming a second resist pattern on said first conductor pattern such that said second resist pattern includes therein a second groove having a second width in conformity with said wiring pattern to be formed;
forming a second conductor pattern on said first conductor pattern along said second groove with said second width while using said second resist pattern as a mask; and
patterning said metal film while using said first conductor pattern as a mask.
Another object of the present invention is to provide a method of fabricating a microstrip line, comprising the steps of:
forming a metal film on a substrate;
forming a first resist pattern on said metal such that said first resist pattern includes therein a first groove having a first with in conformity with a wiring pattern to be formed;
forming a first conductor pattern on said metal film along said first groove with said first width while using said first resist pattern as a mask;
forming a second resist pattern on said first conductor pattern such that said second resist pattern includes therein a second groove having a second width in conformity with said wiring pattern to be formed;
forming a second conductor pattern on said first conductor pattern along said second groove with said second width while using said second resist pattern as a mask; and
patterning said metal film while using said first conductor pattern as a mask.
According to the present invention, a microstrip line is formed with a conductor pattern having a large cross-sectional area suitable for carrying a large current by an electroplating process without inviting increase of capacitance component in the microstrip line impedance.
Other objects and further features of the present invention will become apparent from the following detailed description when read in conjunction with the attached drawings.